Low voltage differential signaling (LVDS) is used for high speed of data transmission with reduced noise and reduced electro-magnetic interference (EMI). Modern LVDS drivers are expected to operate at GHz frequencies. The range of the differential output voltage of the LVDS driver ranges from 250 mV to 450 mV.
When a LVDS driver drives a heavy capacitive load such as a long cable or a high capacitance cable, its frequency of operation has to be decreased to get adequate output voltage differential that conforms to the specified range of 250 mV to 450 mV. To make the LVDS driver capable of operating at high frequency even for heavy capacitive loads, it is necessary to provide pre-emphasis circuitry. This pre-emphasis circuitry provides high driving capability to the LVDS driver at the time of switching, thereby significantly decreasing the charging time of the output load and making it possible to operate at high frequencies.
FIG. 1 shows a low voltage differential signaling driver with pre-emphasis circuit in accordance with U.S. Pat. No. 6,281,715. LVDS driver 100 has a capability of providing output current ID1. The pre-emphasis circuit used with this driver provides an additional current ID2 current at the time of switching making the driver capable of driving the heavy load at a faster signaling rate. The basic driver consists of a current source 10, which is capable of sourcing current ID1. Four NMOS transistors N1–N4 form a current steering circuit. The gates of these four NMOS transistors are controlled by two signals IN and IN˜(both of which are complementary to each other). Resistor 15 establishes a DC voltage to satisfy the high output voltage VOH and low output voltage VOL requirements. The drains of NMOS transistors N3 and N2 are connected to an output pad X. Similarly, the drains of N1 and N4 are connected to output pad Y. Pads X and Y form a differential pair. Both pads are connected to transmission lines (not shown here) and the far end of the transmission line (at the receiver end) is connected to a 100 ohm resistor 16. PMOS transistor P5 forms another current source having its source connected to the supply VDD and its gate voltage is controlled by a bias cell 30. Bias cell 30 makes P5 capable of sourcing current ID2. NMOS transistor N5 acts as a current sink, having its source connected to ground and its gate voltage controlled by Bias cell 30. Bias cell 30 makes N5 capable of sinking current ID2. Transistors P6 and N6 are the control transistors, having their gates controlled by pre-emphasis pulse IXNOR. Pre-emphasis pulse IXNOR becomes high after each input transition. Inverter INV4 generates the complementary signal IN˜. Inverters INV1–INV3 with exclusive-NOR gate XNOR form the pre-emphasis pulse generator. Inverter INV5 inverts the pre-emphasis pulse IXNOR. Transistors P7, N7 and N8 with resistor R2 form bias cell 30. This bias cell bias the PMOS P5 as current source and NMOS N5 as current sink.
Let us consider the case when the input signal is at logic low, i.e. IN=0, so IN˜=1, a=0, b=1, IXNOR=0. Since IXNOR is low, NMOS N6 and PMOS P6 are switched off, so current ID2 is not provided to the output driver 100. In this case NMOS transistors N1 and N2 are on, and N3 and N4 are off, causing current ID1 to flow through resistor 16 from Y to X, setting Y to VOH and X to VOL. Similarly when IN=1, IN˜=0, a=1, b=0, IXNOR=0, turning off pre-emphasis transistors N6 and P6 and providing no current to output driver 100. Since IN=1 and IN˜=0, NMOS transistors N3 and N4 are on, and N1 and N2 are off. In this case current ID1 flows through resistor 16 from X to Y, producing a voltage drop across resistor 16. In this case X is at VOH and Y is at VOL. During DC operation only ID1 produces the output voltage across the pads X and Y. The ID1 current is capable of producing the appropriate differential output voltage (between 250 mV and 450 mV) across resistor 16 (Vod=ID1*RL).
When input IN changes from ‘0’ to ‘1’, ‘a’ becomes ‘1’ immediately but ‘b’ is still at ‘1’ due to the delay provided by the delay chain of inverters INV1–INV3, resulting in a positive pre-emphasis pulse at IXNOR. This pre-emphasis pulse switches N6 and P6 ON and current ID2 is supplied to output driver 100. Since IN=1, IN˜=0, transistors N3 and N4 turn ON and allow current ID1+ID2 to flow through output resistor 16 from X to Y. After the time delay of inverters INV1–INV3, ‘b’ becomes low, which makes pre-emphasis pulse IXNOR low, which turns off transistors N6 and P6, cutting off the ID2 current supply to output driver 100.
Similarly, when input IN changes from ‘1’ to ‘0’, ‘a’ becomes ‘0’ immediately but ‘b’ is still at ‘0’, which produces a positive pre-emphasis pulse at IXNOR. This pre-emphasis pulse switches N6 and P6 on and current ID2 is supplied to output driver 100. Since IN=0, IN˜=1, transistors N1 and N2 turn ON and allow current ID1+ID2 to flow through output resistor 16 from Y to X. In this manner, the LVDS driver of FIG. 1 provides an output current of ID1+ID2 at the time of input signal transitions, making it possible to drive capacitive loads at high frequency. The pre-emphasis pulse generator consists of the inverters INV–INV3 and XNOR gate XNOR.
This design of pre-emphasis is however, not suitable for very high frequency operation. This limitation arises from the fact that the output of the pre-emphasis pulse IXNOR is delayed with respect to the input signal IN by a value equal to the propagation delay of the XNOR gate. In fact, in this arrangement, whatever the circuitry is used to generate the pre-emphasis pulse IXNOR will add some delay with respect to the input signal IN. For operating frequencies up to about 500 MHz this delay of the pre-emphasis circuit is not very significant and may be ignored. However, at higher frequencies of operation, the delay of this pre-emphasis circuit becomes significant. At a frequency of 1 GHz, the pulse period is 0.5 ns and even a small propagation delay of about 100 ps significantly derates the operation of LVDS driver when driving capacitive loads. As an example, assuming the pre-emphasis circuit shows the delay of 150 ps and the operating frequency of operation is 1 GHz, the pre-emphasis current ID2 starts boosting the output driver 100 after 150 ps and has a total of 350 ps to provide this current. In this condition, the LVDS driver with pre-emphasis is not capable of providing the required swing at the output pads X and Y. To compensate for this swing one method is to increase the pre-emphasis current ID2, but this results in an unnecessary increase in the size of transistors P5 and N5. Also this design of LVDS driver with pre-emphasis contains a Bias cell 30 that causes unnecessary power dissipation.